1. Technical Field
The disclosure relates generally to a system and method for static timing, and more particularly to a system and method for adjustment of modeled delay variation as a function of past device state and/or switching history during static timing analysis.
2. Background Art
One dominant form of performance analysis used during integrated circuit (IC) design is static timing analysis (STA). STA is an important process by which one identifies any circuit races/hazards which could cause a chip to malfunction, verifies the operational speed of a chip, and identifies the paths which limit the operational speed. STA typically operates on a timing graph, in which nodes represent electrical nodes (e.g., circuit pins) at which signals may make transitions at various times, and edges, or “propagate segments,” representing the delays of the circuits and/or wires connecting the nodes. Although it may report performance-limiting paths, typical STA methods do not actually operate on paths (of which there may be an exponentially large number), and instead use a “block-based” approach to compute and propagate forward signal arrival times reflecting the earliest and/or latest possible times that signal transitions can occur at nodes in the timing graph. As a result, STA is extremely efficient, allowing for rapid estimation of IC timing on very large designs as compared to other approaches (e.g. transient simulation). STA also provides accurate timing estimates without any knowledge of the function of the design being timed, and therefore can operate in the absence of any specific input signals. However, this last trait makes STA particularly sensitive to delay variation resulting from the past device state and/or switching history, as it results in a lack of availability of information regarding the prior state and/or switching history of the modeled devices. The past device state and/or switching history of a device will hereafter be referred to as ‘device history’, or simply ‘history’.
An important aspect of STA is evaluation of timing tests, which are required ordering relationships between the arrival of signals on converging paths. Common examples of timing tests are setup tests (often represented in a timing graph as “test segments”), requiring that a data signal at an input of a flip-flop or other memory element becomes stable for some setup period before the clock signal transition that stores that data (i.e., that the latest possible data transition in a clock cycle occur at least the required setup period before the earliest possible clock transition for that cycle), and hold tests, requiring that a data signal at an input of a flip-flop or other memory element remain stable for some hold period before the clock signal transition that stores that data (i.e., that the earliest possible data transition in a clock cycle occur at least the required hold period after the latest possible clock transition for the preceding clock cycle). Pairs of paths along which early and late arrival times compared in a timing test are propagated are often referred to as racing paths.
Although STA is typically performed at a particular “corner,” which is a specified combination of conditions such as voltage, temperature, and manufacturing process that affect delays of circuits on a chip, local variations in these and other parameters may cause variations in delays of similar circuits in different locations on a chip. A common way to account for this variation in STA is to compute minimum and maximum delays for circuits, using minimum (or fast) delays to determine early signal arrival times and maximum (or slow) delays to determine late signal arrival times.
The aforementioned variations in device history can be one cause of such delay variation when digital IC's are manufactured using Partially Deleted (PD) Silicon on Insulator (SOI) technology, wherein the device body may be electrically insulated from the substrate. SOI technology can provide benefits such as improved performance and reduced power consumption. However, drawbacks exist as well; one in particular being that devices with PD-SOI technology suffer from a history effect, wherein the performance of a given device can be a function of the state history of that device, as the varying charge stored on the floating body of the device dynamically alters the threshold voltage of the device during operation. One related art method of reducing pessimism due to body charge in PD-SOI is described in U.S. Pat. No. 6,816,824, which also describes in more detail the manner in which the body charge varies due to changes in device state, and which is incorporated herein by reference. The '824 patent describes determining a range of possible body charge or voltage values for a device based on connectivity of a device within a circuit (in particular whether it is tied to a power supply rail), but assumes the most extreme range possible over all possible device histories, and does not consider the actual possible state histories of the device.
An alternate example of delay variation occurring as a result of device history would be switching history based temperature fluctuations. Switching of devices causes power dissipation and local self-heating of the devices (transistors and wires) conducting the switching signals. A device that switches rapidly generates more heat and will heat up relative to its neighboring devices, and this change in temperature can alter the electrical characteristics, and hence the delay, of those devices. Because heat conduction on an integrated circuit is typically slow relative to the circuit switching speeds, this local change in temperature due to switching will typically persist for several clock cycles, so the delay change of a switching event due to switching-induced self-heating will be a function of the switching history over some number of clock cycles immediately preceding the switching event.
Yet another example of delay variation due to device history is negative bias temperature instability (NBTI) in which cumulative switching over very long periods (e.g., the life of the circuit) cause degradation in the performance of PFETs. The degree of degradation depends on the cumulative number of times the device has switched. In this case, the time window over which history must be considered is much longer than for PD-SOI body history or switching-induced self-heating.
Still another example of delay variation due to device history is the hot carrier effect, where the strong electric field across the gate insulator of a conducting FET cause carriers to be injected into the gate insulator and trapped, causing a gradual change in the device characteristics. The degree of degradation depends on the cumulative time the device has been in the on state, and as with NBTI, the time window over which history must be considered is much longer than for PD-SOI body history or switching-induced self-heating.
In all of the preceding cases, some aspect of the history (e.g., switching, state) of a circuit element (e.g., a wire or transistor) over some preceding period (e.g., several clock cycles, or the entire operating history of the device) causes an alteration in the delay of the device.
While sufficiently conservative to ensure working hardware, using a fast/slow delay range that accounts for the full range of possible device history is typically overly pessimistic. While in some cases it may be possible for the modeled fast/slow cases to simultaneously exist (and the timing must ensure functional hardware in this event), this will only rarely be the case. This pessimism places an artificial constraint on the performance of the integrated circuits (ICs) produced, scaling back the potential physical performance as a result of design tool limitations. Therefore, it is desirable to have an approach that can leverage any available device history knowledge in order to adjust the device history based delay component, typically with the goal of reducing pessimism.
One related art means of reducing pessimism in STA is through the Common Path Pessimism Removal (CPPR) approach described in U.S. Pat. Nos. 5,636,372 and 7,117,466. CPPR removes the part or all of the fast/slow delay difference from arrival time differences computed at timing tests between paths sharing common portions or parametric dependencies. However, CPPR requires enumeration of sub-paths with exponential complexity, typically allowing only a subset of all possible paths to be checked. As such, this approach is limited in application and is costly, and so it would be preferred to directly limit the pessimism in all tests during the base timing step. CPPR also applies only to pessimism due to correlations between delays in racing paths, while more refined knowledge of history may reduce the fast/slow delay range of a circuit independent of its involvement in any racing paths. Note that this would also reduce the number of tests and paths requiring CPPR as a result of the improved slacks it would generate in the base timing.
The illustrative aspects of the present disclosure are designed to solve the problems herein described and/or other problems not discussed.